As silicon carbide moves deeper into high-volume power semiconductor manufacturing, wafer quality is no longer evaluated only by crystal defects, resistivity, thickness, or surface roughness. Surface cleanliness after polishing and cleaning is becoming increasingly important, especially for substrates intended for epitaxial growth.

A recent 2026 study on 6-inch conductive 4H-SiC substrates highlighted a surface issue known as Time-Dependent Haze, or TDH. Unlike defects that are immediately visible after polishing, TDH may gradually appear after a wafer has been cleaned and stored for a period of time.

This makes it particularly relevant for SiC substrate suppliers, epitaxy companies and device manufacturers.

What Is Time-Dependent Haze?

A wafer may appear clean immediately after final cleaning but later develop haze, particles or other surface abnormalities during storage.

The 2026 research investigated conductive 6-inch 4H-SiC substrates and found that the phenomenon was strongly related to surface residues remaining after cleaning.

The study identified several inorganic ionic residues, including chloride, ammonium and sulfate ions, as important contributors to haze formation.

Instead of remaining permanently dissolved or being completely removed during rinsing, these residues can remain in surface oxide or damaged layers and later produce visible contamination or recrystallized particles.

This means that a wafer passing an initial visual inspection may not necessarily maintain the same surface condition after transportation or storage.

Si-Face and C-Face Behave Differently

One particularly interesting result is that TDH does not develop in exactly the same way on both sides of a 4H-SiC wafer.

The carbon face showed a significantly higher tendency toward time-dependent haze than the silicon face in the reported experiments.

The C-face tended to develop more diffuse haze, while defects on the Si-face were more likely to appear as concentrated particles.

This difference demonstrates an important characteristic of SiC processing: crystal orientation and surface termination can influence cleaning, polishing and contamination behavior.

For semiconductor customers, therefore, simply specifying “double-side polished SiC wafer” may not always be sufficient. The surface condition and intended functional side should also be clearly defined.

Why Surface Cleanliness Matters Before Epitaxy

High-quality SiC epitaxy requires an extremely controlled substrate surface.

Residual contamination can influence:

• epitaxial nucleation and growth;

• local defect formation;

• interface quality;

• particle counts;

• downstream device yield.

For applications such as SiC MOSFETs, Schottky diodes and other high-voltage devices, maintaining a stable epi-ready surface is essential.

As wafer diameters increase and production volumes grow, even small variations in surface cleaning can become important sources of yield loss.

Cleaning Is Only Part of the Quality Equation

The study also shows why wafer quality should not be evaluated only immediately after manufacturing.

For an epi-ready SiC substrate, several stages can affect the final surface condition:

wafer polishing → final cleaning → inspection → clean packaging → transportation → storage → unpacking → epitaxy.

Contamination introduced or activated at any point in this chain can influence later processing.

Therefore, substrate manufacturers increasingly need to consider not only how clean a wafer is when it leaves the factory, but also how stable that surface remains before it enters the epitaxy reactor.

What Buyers Should Consider When Purchasing SiC Wafers

For research laboratories and semiconductor manufacturers purchasing 4H-SiC substrates, specifications such as diameter, thickness and resistivity remain important, but they should be considered together with surface requirements.

Typical specifications may include:

• 2-inch, 3-inch, 4-inch, 6-inch or 8-inch diameter;

• N-type conductive or semi-insulating material;

• Si-face or C-face;

• on-axis or off-axis orientation;

• single-side polished or double-side polished surface;

• epi-ready polishing;

• surface roughness;

• TTV, bow and warp;

• micropipe and defect requirements;

• cleanroom packaging.

For epitaxial applications, surface particle control and packaging condition can be just as important as the basic crystal specifications.

SiC Wafer Quality Is Moving Beyond Crystal Growth

The silicon carbide industry has spent years improving crystal diameter, reducing micropipe density and increasing usable wafer area.

The next stage of competition will increasingly involve surface preparation, polishing, cleaning, contamination control and wafer-to-wafer consistency.

Time-dependent haze is a good example of why advanced SiC manufacturing must treat surface quality as a complete process rather than a single inspection result.

As 6-inch and 8-inch SiC manufacturing expands, stable epi-ready surfaces will become increasingly important for both substrate suppliers and device manufacturers.

For customers evaluating SiC wafers, attention to surface cleaning, storage stability and packaging may ultimately help reduce problems long before epitaxial growth begins.